Austin talks with Ravi Mahajan, a distinguished engineer at Intel Foundry, about the deep history of Intel’s EMIB packaging technology. Ravi explains how the technology originated in the early 2000s to solve for IO density and die disaggregation, the technical hurdles in bringing it to high-volume manufacturing, and how it differs from alternatives like CoWoS. They also touch on the future of packaging, including co-packaged optics.
This episode is presented by Crusoe.
Crusoe’s Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour.
About $2 buys roughly 5M training tokens on smaller models.
Get $5 in credit to start: https://semidoped.com/crusoe
Things we cover:
EMIB’s origin story and early development
The key differences between EMIB and CoWoS
EMIB T, EMIB M, and the potential for active bridges
The industry-wide Heterogeneous Integration Roadmap
Intel Foundry’s work on top-side optical interconnects
This podcast is lightly edited for clarity.
Introduction & Pathfinding at Intel
Welcome listeners to another episode of Semi Doped. I’m Austin Lyons with Chipstrat and with me is a special guest. We’re talking with Ravi Mahajan today. He is a distinguished engineer and the director of the Technology and Pathfinding Group in the Advanced Packaging Technology and Manufacturing Division at Intel Foundry. So Ravi, thank you so much for coming on to talk with us.
Ravi: Austin, thank you for inviting me. It’s a real pleasure. I really appreciate you taking the time and inviting me.
Yes, awesome, great. So, we are going to talk a lot about EMIB today, which I’m super excited about because I think most people are fairly familiar with EMIB today, but they’ve probably only heard about it in the last year or two. And I know that you’ve been working with EMIB and on EMIB since way back in 2007 or something. So I kind of want to go back to the beginning and trace Intel’s history with EMIB, what problem you were trying to solve and why you came up with EMIB and just kind of work all the way through so that people can get a nice appreciation of EMIB and how it’s interesting and everything. But maybe first, to start us off, tell us more about you. You have a nice long title and I know you’ve been at Intel for a long time. So explain more to us what you do day in and day out.
Ravi: Okay. So I’ve been at Intel for 34 and a half years. And I joined studying reliability of packages, then I led the thermal group. And for the longest time, I helped figure out how to cool parts. I still dabble in that area. And just a little bit of history, today, laptops are cooled by heat pipes. When I started work, the max power dissipated was four and a half watts and there were no laptops. Today, we easily cool more than a kilowatt and heat pipes are normal. Everybody accepts them as a feature now. My point is, I’ve been working on cooling devices for a very, very long time and that’s what got me my start in the industry. In the year 2000, I was asked to lead the pathfinding effort in Intel. Essentially, look out in the future and plan so that we have technologies ready, mature, understood and narrowed down for them to go into production. And I’ve been doing this ever since. Right now, I lead the pathfinding group. We look roughly three to five years out and get Intel ready for what comes in the future. And I do this both as an Intel employee, also as a industry sponsor of a roadmap, the heterogeneous integration roadmap that IEEE, Semi and ASME, collaborate on.
Interesting. Okay, tell us just a little bit more about that last, the IEEE group. Who all participates and what is the purpose of it?
Ravi: So, it is very evident now that heterogeneous integration where you take different components that are designed on separate platforms and stitched on a compact packaging platform, but a compact system, bigger picture, is the way compute communications are going to move forward. And you see this everywhere. So, in the year 2016, when the silicon driven roadmap, the ITRS came to an end, quite a few people got together and said, we ought to have a systems driven roadmap for electronics. If we collectively project a direction that we agree on, then everybody, architects, designers, assembly houses, equipment, materials, all of them, can all converge on a common direction and that way we are ready for the future. So, IEEE sponsors this primarily, Semi contributes, and because Semi is a very good voice in the industry, people listen to what they do along with IEEE that offers technical heft. And then ASME, the American Society of Mechanical Engineers also contribute. We also are building connections with other groups, for instance, GEA and we are collectively writing a roadmap for the future. It is non-confidential, it is strategic and it is essentially driven by volunteers. Lots of technologies from across academia, industry come together. And because it’s non-competitive, it’s a very good venue for people to talk about how we define our futures.
Nice, awesome. Okay, that’s cool because I think that puts what we’re going to talk about EMIB in even a bigger perspective, which is the whole industry has to come together to work on these challenges. It’s not just one company at a time and you pointed out it’s not just the design companies, but it’s also the manufacturing and everyone in between, even to the point of materials, which is pretty interesting. And even academia as they’re looking five to seven years ahead.
The Origin of EMIB
Let’s go all the way back, 2007. I believe roughly around then, and you can correct me if I’m wrong, you published a paper and EMIB was becoming a thing all the way back then. So maybe explain to listeners what EMIB even stands for and then take us way back and help me understand what problems you were trying to solve back then and how EMIB came about.
Ravi: The acronym stands for embedded multi-die interconnect bridge. It originally started out, I called it a silicon patch when I started this a long time ago. A little bit of history, it goes before 2007. We in Intel like to synchronize technology development so that we are ready to jump into high volume manufacturing together. So, silicon packaging and system interfaces all have to move in lock step. The best way to do a roadmap is to align milestones. And in those days, we agreed that we should align to the silicon node milestones, which means when 90 nanometers is ready, the packaging associated with 90 nanometers is ready. Same story with 65, 45, 32, 22, etc. So, then this brings a natural question. Silicon has a roadmap, the nodes progress at a steady cadence. What attributes on the package should we change to progress at that cadence? That was the question.
And there’s many things you can do, packages gen over gen cool better, deliver power better, they become thinner, right? If you remember in that time frame in the early 2000s, laptops were becoming very popular. Everybody wanted thinner, lighter laptops, cell phones, all that kind of stuff. The one area I will focus on in this discussion is interconnects. We do C4 interconnects, which essentially means you take bumps on a die and connect it to pads on a package. Those pads are connected to wires that escape through the edge of the die. So you have two natural attributes. The number of bumps per unit area, for some reason, people call them IO, so I’ll also call it IO. Bumps per millimeter square or IO per millimeter square. And the other attribute that I was interested in was number of wires that escape the edge of the die, IO per millimeter. And because a package is multiple layers, you have to normalize it, so you do IO per millimeter of die edge per layer of the package. So think of the wires that escape the edge of the die.
To start creating a roadmap, you have to look at your history and then project the future. So I went back all the way to the 90 nanometer node and I started just calculating and plotting how many wires escape the edge of the die. And I created a plot. It’s pretty interesting. It turns out that generation over generation, we were getting 10% better, roughly. It’s very nice to see something fit on a plot and when you look at it at a plot, you wonder why is it 10%? Why not 5%? Why not 20%? So that sparks some intellectual curiosity. So I asked myself, why not more? What happens if you do more? And then I realized that in organic packages, you print using certain lithographic techniques. Silicon, you can print much finer wires. So if there was a way by which you could do silicon wires instead of package wires or do silicon and package wires, perhaps you have a path to increase IO density. So that’s one vector, that was one train of thought.
The second thing was, as you try and integrate heterogeneous components, you want to stitch them on a package and you also want to reduce your die size, so you get the benefit of cost, the yield gets better as die size shrinks. So there’s quite a few people who wanted to disaggregate die and stitch them together. And the first people who came to talk to me were the FPGA guys, because the FPGA guys often times take all kinds of interesting devices and stitch it on a package. And they want low power, high density interconnects in quite a few cases. So, this whole idea of disaggregation also was in parallel or simultaneously evolving.
In 2007, there was somebody who came to visit us, an architect, and he asked us if we could split the die into smaller parts and stitch them. He was asking us for what is today called fan-out wafer level packaging. So I showed him my idea and he liked it. He said, great idea, but he realized it was really far-fetched. It was almost science fiction in those days. So, I presented it to him and then I walked out of that room thinking, it’s not a bad idea. I should do something with it. So, I should highlight two important people in this, Bob Segman, former Intel fellow, and one of the smartest people I’ve worked with in packaging. And then Devendra Malik, who was a colleague of mine, also among the smartest people. All three of us were thinking along these lines. So I go to Devendra Malik and I showed him this idea and he says, not a bad idea, you should file a patent for it. So, then I said, I’m taking a piece of silicon, putting it in an organic package, the expansion mismatch is quite high. What happens if it cracks? So I went to another person, Sandeep Sunny, and he said, why don’t you cushion it? Why don’t you put a soft pad underneath it so that it is decoupled from the package? And that was a pretty good idea. So, Sandeep and I wrote the first patent for EMIB. This was like an open cavity bridge, we said, why don’t we create cavities, put silicon in it, cushion it with a pad, and then attach die on top, because we get fine wires, perhaps we make the pitch finer, so you get a lot more interconnect. And you only get this by this idea, you get interconnect only where you need it. So you don’t take the entire area and make interconnect, which is a difference from the silicon interposer. So you have localized interconnects only where you need it. And that was the genesis of this idea. A few people who I talked to and I submitted this patent and the rest as you can know is history now. Everybody’s picked this idea up.
So back then in the early 2000s, you were both asking, how can we increase IO per millimeter squared, like IO density? And at the same time, the industry and other people were asking how can we disaggregate from these monolithic chips and actually go toward as people know of them as chiplets. And all the benefits that chiplets entails, but of course, to do that, you’ll need to be able to, quote unquote, stitch together these die. And so it’s kind of simultaneously, you’re thinking about the packaging and people are asking and have a need for it. And tell me, at the time then, was the default way to stitch it together to use an organic substrate?
Ravi: Two things, one is IO per millimeter square, which is the pitch, which you scale down, and then IO per millimeter, which is the wires that you scale. So both of them were important. One is lateral, the other is vertical. And the default was organic. And even then the pitches we were going after were pretty state of the art. I mean, very, very challenging to do as is and EMIB added another layer of complexity to this business.
Yes, yes, got it. So what ultimately drove you to look to silicon instead of—was it just it was going to be hard enough with organic as is and silicon was a clever way to let you design even tighter pitches or why did you first reach for this the silicon bridge idea?
Ravi: What attracted me about the silicon bridge idea was you do localized interconnects, which means not all parts of the die need to be fine pitch. And in fact, fine pitch wires are not a great idea to deliver power. So there have to be large portions of the die that use thick wires or fat wires and then local areas that use fine wires. So you decouple high speed IO from power. And so I thought, why not kill two birds with the same stone, develop something that’s localized for IO and then leave the rest of it untouched.
Okay. So keep the big fat cheap wires for delivering power and then use the fine pitch, probably expensive, but you could get them small and densely packed together for the high-speed IO.
Ravi: And the expensive part you can get away with by doing just small patches. So it’s really easy to build a wafer and take small strips out of it. You get a lot of those strips. So the cost is mitigated by doing a bridge.
From Patent to Production
Yes, okay. So you came up with this idea, filed the patent. It was complicated, but you had help in coming up with ways to think about decoupling it from the substrate and dealing with thermal mismatch and other complexities. How did you go from, what was the story in going from a patent to actually building it to eventually manufacturing it at scale?
Ravi: That’s a good question. When first envisioned, this was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that. And then there were many enabling technologies that had to come along. So I’ll list them one by one. The idea said we need four thick metal layers, two microns thick on a silicon process. Typical silicon processes do one or two. I wanted four. So we had to develop a passive silicon process that stacked four thick metal layers. We had to figure out a way to thin and handle these die.
And to continue my story about the bridge, Intel had invested in embedding around the same time. We had something called bumpless build up layers where we were building layers out and we were learning how to embed stuff. So somewhere along the way we said, it’ll be pretty smart if we embed the die as well, like these thin strips. So that says you have to learn the embedding process, place them precisely. And we are talking about approximately 5,000 bumps in a very, very tiny area, very fine pitch. So that embedding has to happen. Then you have to create a joint where you put fine pitch bumps with small amounts of solder adjacent to coarse pitch bumps with a lot of solder. So imagine trying to squish all of them together and all of them have to form a joint. So you have to control the solder, you have to control the attached process, so thermal compression bonding. That had to come along.
And if you do fine pitch wiring on silicon and you send signals along, you have to boost them every 500 micronish with active silicon. But here we are talking about a 6 mm long wire with no ability to boost. So you had to design it so that the signal integrity was retained. That was another thing we had to work on. So quite a few of these things had to come along, the equipment, the process, the materials for the die attach film, all that had to come along. And that was maturing in parallel for different applications. We lined it up for our application and around 2011, 12, when it was obvious that this was a very good solution and needed for cost and performance, we started building parts and in 2012 was the turning point. People realized, hey, there’s real value here. Let’s figure out how to build this.
That sounds complicated. You had to figure out how to make these tiny little bridges, how to embed them, how to put bumps on them and eventually connect them, probably get the alignment just perfect. You had to think about signal integrity, and it sounds like lots of industry innovations were happening in parallel, even from a tool perspective.
Ravi: So 2012 was the year in which we started taking it from PowerPoint into actual labs. And then 2012, 2013 were the years where we got everything together, the equipment, the process, the materials, the design. I should point out one more thing. Chiplets use standardized interfaces. So we had to design the bump patterns and the wires to conform to a standardized link, in those days AIB was the link and today it’s UCIe that superseded AIB. So we had to design it so that it met AIB requirements and today we design it to meet UCIe. So there was a design component to this whole thing.
Yes. So then how did it go then? Like when did it finally make its way into high volume manufacturing and what was the first use case? Was it the FPGAs or was it HBM? I feel like I read about that somewhere.
Ravi: It was the first use case. There were two parallel use cases. There was an FPGA with HBM use case and there was a graphics chip Intel was designing that also used HBM. The year 2013 was spent really understanding the nuances of manufacturing. 2014 was when we were convinced now that we could build enough to tell us how to scale it in HBM. So middle of 2014 Intel announced this. August 2014 if I’m not mistaken. We announced to the world that we have this technology and we know what it takes to make it and then we started putting in infrastructure to ramp it.
Got it. So you were almost a decade in and thinking about it until the point where you actually announced it. Yeah, which I think just goes to show that it’s complicated and it also makes me think, I wonder what you’re working on now that you’re going to announce seven years from now.
Ravi: I just wanted one more nuance, Austin, it’s important to recognize: solder volumes. So large solder and tiny solder. Now tiny solder volumes have a problem with electromigration as in you don’t just have enough. So you have to first squish them and when you heat them over and over again, they electromigrate, you form intermetallics, they become hard. So we solved that problem as well by containing and designing the volume of solder for those pitches, which I think is a technological marvel.
Amazing. Which how how many people were working on this at that time, would you say?
Ravi: My original team was seven people in 2013. It expanded to about 150 to 200 in 2014 by the first half of 2014. And then we had multiple groups of people who came in to work in suppliers as all of them.
Yes, because it sounds very cross-disciplinary. Okay, so why was HBM a first application that needed EMIB, needed these local silicon bridges embedded for the fine pitch and everything?
Ravi: So if you go back to that time, there were three application spaces that really would have loved to have fine pitch interconnect. One was FPGA because they do all kinds of heterogeneous die and they wanted HBM to give them local memory. And the value of HBM is you get high bandwidth interconnects and you also get high capacity DRAMs in parallel. And it is designed to be a low power, high energy efficiency bus. There was a competing technology called Wide IO2. The mobile application also wanted local DRAMs and they were focused on optimizing Wide IO2 for mobile. And then the GPU applications wanted HBM because they wanted to put a bunch of HBMs next to the compute. You see those designs today. So they wanted access to a lot of memory, high bandwidth, low power. So there were three competing markets and we did our math internally and we figured that if you get the highest performing designs, then you can waterfall everything down and that’s why we picked HBM.
Got it. So HBM would be the most demanding use case and if you can make EMIB work for that, then it’ll work for everything else.
Ravi: Yeah. We had to pick the memory, and with HBM you have to attach many HBMs. We started with four and I think we just scaled up over time.
EMIB vs. CoWoS
Yes, totally. Okay, so this is a fascinating history from the idea all the way through the early applications. Now, I think is a good time to jump into talking about TSMC’s CoWoS, or just CoWoS in general, which is a way to package and interconnect dies and help the listener understand, because I think a lot of people have heard about it. Generally, they hear about CoWoS is a bottleneck, there’s not enough CoWoS capacity, so on and so forth. Help people understand some differences or similarities between CoWoS and EMIB.
Ravi: Let me first describe CoWoS in very simple terms. The idea is that you take a silicon interposer with similar pitches and similar wiring densities as EMIB. So think of it as, let’s say you have a rectangle and you put multiple die on top of it. Now the total die area that you can put on that rectangle, it has to be smaller than the size of the rectangle. So if you want more and more die, you have to increase the size of the base. And so what happens is, it’s a great technology. But what happens is as you increase the size of the base, you get fewer and fewer die out of a wafer. So in today’s AI HPC world where people want a lot of interconnects, they want a large CoWoS base. That’s why you hear terms like 2X reticle, 4X reticle. So the size increased. That’s one thing. It’s a great technology, but it has this particular scaling concern.
The second thing is you connect a die and you send a signal through through silicon vias in the interposer and then they connect to the package. The pitch of the interposer to package has also to be carefully designed for reliability. That’s the other thing. Also, you’re adding an extra length in signaling through this. The third thing is you compel the die pitches to be roughly uniform and every aspect of the die to have to deal with fine pitch interconnects underneath, not just in the IO regions.
EMIB on the other hand has got much lesser silicon area. So you can get many bridges. You can decouple your silicon manufacturing process for the bridge and the embedding process from the attached process if you will. Imagine you make a bunch of bridges, you slice the wafer, thin them, slice the wafer, send it to a substrate manufacturing line to embed in there. Whatever losses you take, don’t get compounded with the loss of the assembly at the end. There is no size or scaling limitation because you’re not worried about the size of the base if you will. You’re no longer restricted by the size of the base. You can put more and more. That’s why you see packages with 16, 20ish bridges and the size of the package is pretty large. EMIB is easily scalable to a panel scale process. So you can imagine a panel with larger and larger packages with more and more bridges. So the way I look at it is interconnections where you need them and only where you need them.
Okay. This is a differentiator. Yes, let me reflect it back. So, when I think about CoWoS style, I’m thinking about an interposer that ultimately, it’s like there’s a substrate is the base layer, and then I’ve got this interposer layer, and then I put the die on top, and the connections go from the die through the interposer over to the other die. And your first point was that when I want to design a system, let’s say maybe with two GPUs on it, or four GPUs on it, plus HBM for everything, it’s going to be bigger in area because of your reticle size, compute dies, plus a bunch of maybe HBM and IO and whatnot. And that requires the interposer itself to continue to get bigger and bigger that they sit on and connect. And so your point was, when I’m creating that interposer, the wafer that it’s coming from, obviously that interposer itself is taking up more and more of the wafer that it comes from. As opposed to EMIB where the little silicon bridges are made and diced separately, and then the substrate instead of attaching, instead of an attached step where you’re attaching an interposer and kind of attaching the die on top of that. For EMIB, it’s an embed step where you’ve got the substrate and you need to just take these tiny little die, which is not trivial to do, but you take the little bridges and you embed them in the right place. And then you’re ultimately putting the die right on top of that substrate. So instead of like three layers tall, it’s two layers tall with the silicon bridges embedded. And then to your point, this can scale to however large is needed because again, then at that point, it’s just about the substrate scaling and properly embedding the little bridges. And so for example, maybe the substrate’s even a big panel or something. But it just inherently you’re because you’re taking little bridges and putting them where you need them, that sort of scales indefinitely if you will.
Ravi: Yeah, it’s localized interconnect bridges where you need them and standardized interconnects. You have standardized bridges.
Yep, that makes sense. So how should we think about yield in terms of EMIB? When people talk about EMIB’s yield, it feels like just taking silicon and dicing up and getting lots of little bridges, that doesn’t seem the hard part where there would be yield concern. Is the tricky part actually the embedding step?
Ravi: That’s what took the most of our energy to figure out a way by which you embed them and get the yield up. So get the right class of equipment to do the embedding right. And then once you have a substrate with an embedded or multiple embedded bridges, how do you do the attach where you have coarse pitch attach in the central regions and localized fine pitch attach at the edges? And that’s where I’m really proud of the team that worked on it because these guys developed models, they figured out how to get all of this down to a T. How to embed, how to attach, how to manage the process, control the attach process. That’s like a really fascinating engineering exercise.
The EMIB Portfolio and Foundry Model
Yeah, very impressive. What fun work for people who work at Intel Foundry to work on too. Those are good challenges. So, EMIB is very fascinating and we’re talking about it in terms of AI accelerators, for example, because I think that’s what everyone can relate to today. Are there other use cases for EMIB? I mean, ultimately, will everything be using chiplets and needing EMIB?
Ravi: Everything would use chiplets. Not all of them will need EMIB. So if you take UCIe as an example case, UCIe has two forms. There is UCIe-S, which is standard organic packages—nothing special needed in terms of bridges or others—and there is UCIe-A. So the idea of chiplets goes past the idea of EMIB itself. But EMIB is an important enabler for chiplets. And the other thing is, CoWoS can enable chiplets just as well. You can design chiplets in both of them. And just like you use bridges only where you need them, you use CoWoS when you need it. So you have now a pretty good set of options, like a portfolio that you can pick and choose from.
Got it. So now I know there’s now in the last couple years, there’s been newer versions or flavors of EMIB, so to speak, EMIB T and EMIB M. What are those and why was the original EMIB not enough?
Ravi: Actually the original EMIB patent had everything. It had M, it had T, all flavors.
Oh, okay.
Ravi: Yeah. But when we started building it, we thought it was easier to develop a technology complex as it was without the through silicon vias. Now what happens in that bridge is you have to wrap around the bridge to deliver power. So power delivery is a bit torturous, but it’s not that big a deal, but it is torturous in design. If instead of wrapping around the bridge, if you deliver power straight up, which is what EMIB T does, you have an advantage. You can do multiple power rails and you can control voltage and eventually you can control power. Embedding the MIM cap technology, which is essentially capacitors and metal layers is something that we have had for a very long time. So it seems like a natural thing to add it to the bridge as well and offer local improvements in power delivery performance, like a local capacitance for local voltage droop management. So that’s a natural version of EMIB as well.
Got it.
Ravi: There’s one more version I should point out. Austin, sorry to interrupt, but why does the EMIB have to be passive? Why can it not be active as well? So, and we published a paper last year where we showed that if you put simple repeater circuits, you can even boost a signal as it goes through the length of the bridge. So that’s another variant that they can work on.
What’s the use case there? Is it really big chips or something? SOCs?
Ravi: Well, there were two or three use cases. Architects always get interested when they see ideas like this. They wanted to distribute IP. Somebody wanted to send it over longer lengths. And I felt that if we have the core technology enabled, we can show what it is capable of and then architects can use it the way they want.
Sure. So, EMIB T through silicon vias and EMIB M with the MIM capacitors, metal insulator metal capacitors, and this sort of active EMIB, all of these are really just tools that the foundry is giving to the designer to help them better manage power delivery and maybe do other innovative things.
Ravi: Yeah. At different levels of maturity, obviously, the EMIB T will take a lot more work, but the existence proof is there. So we published it last year to show what you can do if you had an active, how to do an active bridge.
Got it. Nice. Okay, so now I know that Intel Foundry, obviously, the last several years have been very interesting for Intel and for Intel Foundry and for us ecosystem watchers with foundry taking on more and more of a focus on external customers and not just being a captive foundry for an IDM. And I know that Intel Foundry has said quite often, hey, we will package dies from any foundry. You could use Intel Foundry for packaging, but you don’t necessarily have to use it for your logic die. Of course, you can if you want, but Intel Foundry is willing to package dies from anyone else. So I’m curious, as that relates to EMIB, is that harder for any reason or is it not conceptually just it doesn’t matter where the die comes from, the technology is the same?
Ravi: It’s not harder necessarily, conceptually very similar. You just have to make sure that the specs of the die that comes in for packaging meets what you require for your assembly process. But conceptually not much harder. Just different, that’s it.
Yep, that makes sense. And so then maybe relatedly, as I’m thinking about Intel taking dies from other people, if alternatively, do other OSATs or anyone have the ability to do EMIB or is that an Intel Foundry only technology?
Ravi: Yeah, Intel Foundry is the only foundry packaging EMIB today. And we have a pretty robust ecosystem that enables this packaging with EMIB.
The Future of Packaging
Okay, yep, makes sense. Okay, so now maybe catch us up on the, we talked very early on about your role in the broader industry with the heterogeneous integration roadmap. As you’re sitting in that position, and just being a pathfinding person always looking ahead, what is the industry’s biggest packaging gap, looking forward beyond EMIB?
Ravi: So the way we did this roadmap was to have a systems focus and ask what kind of systems are going to
Yeah, amazing. It does sound so again, multi-disciplinary and complex. Obviously, packaging is no longer just about electrical. It’s obviously electrical, thermal. You talked about power. You talked about materials, material interfaces. Even EDA, of course, being able to simulate all of this. I guess, maybe on that topic, last question, recently I talked to Synopsys and they’re thinking a lot about agentic AI. And you’re obviously pathfinding and doing kind of basic research and thinking further out, but is AI and agents coming into your workflow or the industry’s workflow at all, even at a pathfinding perspective?
Ravi: Yeah, in a couple of ways, Austin. The one is, I also have heard similar talks from Synopsys, Cadence, Siemens, and we seem to be talking the same language. AI can be utilized to pick optimization paths faster. You can also use it intelligently in manufacturing to distill out yield loss mechanisms and then filter them out of the system. So there’s a lot of opportunity to use AI to accelerate design and eventually create digital twins in a real sense, predictive digital twins that tell you what will be the state of stress of a structure as a function of time, reliability, exposure, and then design something that fits within a reliability envelope. So there’s a lot of value in many aspects of semiconductor packaging for AI to be used.
Optical Interconnects
Yeah, fascinating. Okay, so so far we’ve been talking about essentially electrical interconnects, at very small scale, with EMIB and Intel has 20 years of history here, which is incredible and amazing. And when you describe how complex it is, of course, it took 20 years because it’s very complicated and now it’s very robust and in production. Now, a lot of there’s a lot of talk in the AI era about other interconnects, optical interconnects, of course, being one. And I know that Intel Foundry has some experience over time with optics, silicon photonics, that kind of thing. Is there anything in that realm that you have been working on or your team has been working on that you’re able to talk about?
Ravi: Yeah, I can let me start conceptually first. If you look at what a package does, essentially it has lateral connections on the surface of the package that connect different components and then connections that go through the package to the motherboard, if you will, or the PCB. What if we could increase the bandwidth capability of the package by building complementary optical interconnects? So, what if you could use the top surface of the package to send light in and out? So that way you look at the package and you say, how much bandwidth do I eke out of it? You get a lot more because you get a lot of bandwidth density. You have to learn how to attach an EIC to a PIC. You have to figure out how to integrate the light sources, make sure they’re reliable, make sure that the interface between the photonics IC and the system connection has a scalable path.
So, I’ve published quite a bit in this area. And I am convinced that if you do this right, optical will significantly improve the bandwidth you get in and out of a package. So we focus mainly on top side optics today. That’s what our publications have been. And the ecosystem is maturing quite a bit, Intel has a fab that does photonics ICs. We know how to do attach and we’ve demonstrated high yielding attach in some regions. So, we are internally maturing quite well.
Amazing. And ultimately, is that top side, optical attach, optical fibers coming in, bringing obviously increasing the IO bandwidth significantly there. Is that primarily in die-to-die applications or is that connecting to other chips or to a switch or something?
Ravi: Package to package is where I think it will—we have near package optics today and we have transceivers, pluggables. Eventually, and I hope it happens sooner than later, you will have co-packaged optics for power and density reasons. But it will be package to package.
Gotcha. Okay, fascinating. Well, I think we’ll have to do another conversation sometime where we can go deep into that because it’s very interesting and I’d love to learn more from you on that. But with that, we are at time. So thank you listeners. I hope you learned a lot. I hope that you have a great appreciation now for Intel’s EMIB history and some of the benefits of EMIB. And Ravi, thank you so much for your time today.
Ravi: My pleasure. Thank you for having me.
Anytime.
